Verify presence of the default “golden” shell using xbmgmt examine –verbose
paolini@aptd:~$ sudo /opt/xilinx/xrt/bin/xbmgmt examine --verbose
Verbose: Enabling Verbosity
Verbose: SubCommand: examine
System Configuration
OS Name : Linux
Release : 5.4.0-135-generic
Version : #152-Ubuntu SMP Wed Nov 23 20:19:22 UTC 2022
Machine : x86_64
CPU Cores : 128
Memory : 515894 MB
Distribution : Ubuntu 20.04.5 LTS
GLIBC : 2.31
Model : R282-Z93-00
XRT
Version : 2.14.354
Branch : 2022.2
Hash : 43926231f7183688add2dccfd391b36a1f000bea
Hash Date : 2022-10-08 09:49:58
XOCL : unknown, unknown
XCLMGMT : 2.14.354, 43926231f7183688add2dccfd391b36a1f000bea
Devices present
BDF : Shell Platform UUID Device ID Device Ready*
----------------------------------------------------------------------------------
[0000:81:00.0] : xilinx_u280_GOLDEN_8 n/a n/a No
* Devices that are not ready will have reduced functionality when using XRT tools
Then flash the base image using xbmgmt program –base –device 0000:81:00.0 –image /opt/xilinx/firmware/u280/gen3x16-xdma/base/partition.xsabin
paolini@aptd:~$ sudo /opt/xilinx/xrt/bin/xbmgmt program --base --device 0000:81:00.0 --image /opt/xilinx/firmware/u280/gen3x16-xdma/base/partition.xsabin
----------------------------------------------------
Device : [0000:81:00.0]
Current Configuration
Platform : xilinx_u280_GOLDEN_8
SC Version : INACTIVE
Platform ID : N/A
Incoming Configuration
Deployment File : partition.xsabin
Deployment Directory : /lib/firmware/xilinx/283bab8f654d8674968f4da57f7fa5d7
Size : 135,050,025 bytes
Timestamp : Sun Dec 4 21:36:42 2022
Platform : xilinx_u280_gen3x16_xdma_base_1
SC Version : 4.3.28
Platform UUID : 283BAB8F-654D-8674-968F-4DA57F7FA5D7
----------------------------------------------------
Actions to perform:
[0000:81:00.0] : Program base (FLASH) image
----------------------------------------------------
Are you sure you wish to proceed? [Y/n]: y
[0000:81:00.0] : Updating base (e.g., shell) flash image...
Bitstream guard installed on flash @0x1002000
Persisted 716129 bytes of meta data to flash 0 @0x7f51273
Extracting bitstream from MCS data:
...............................................
Extracted 48844316 bytes from bitstream @0x1002000
Writing bitstream to flash 0:
...............................................
Bitstream guard removed from flash
INFO : Base flash image has been programmed successfully.
----------------------------------------------------
Report
[0000:81:00.0] : Factory or Recovery image detected. Reflash the device after the reboot to update the SC firmware.
[0000:81:00.0] : Successfully flashed the base (e.g., shell) image
Device flashed successfully.
****************************************************
Cold reboot machine to load the new image on device.
****************************************************
After a cold reboot, verify presence of new SC firmware and device is ready:
paolini@aptd:~$ sudo /opt/xilinx/xrt/bin/xbmgmt examine --verbose
Verbose: Enabling Verbosity
Verbose: SubCommand: examine
System Configuration
OS Name : Linux
Release : 5.4.0-135-generic
Version : #152-Ubuntu SMP Wed Nov 23 20:19:22 UTC 2022
Machine : x86_64
CPU Cores : 128
Memory : 515894 MB
Distribution : Ubuntu 20.04.5 LTS
GLIBC : 2.31
Model : R282-Z93-00
XRT
Version : 2.14.354
Branch : 2022.2
Hash : 43926231f7183688add2dccfd391b36a1f000bea
Hash Date : 2022-10-08 09:49:58
XOCL : 2.14.354, 43926231f7183688add2dccfd391b36a1f000bea
XCLMGMT : 2.14.354, 43926231f7183688add2dccfd391b36a1f000bea
Devices present
BDF : Shell Platform UUID Device ID Device Ready*
---------------------------------------------------------------------------------------------------------------------------
[0000:81:00.0] : xilinx_u280_gen3x16_xdma_base_1 283BAB8F-654D-8674-968F-4DA57F7FA5D7 mgmt(inst=33024) Yes
* Devices that are not ready will have reduced functionality when using XRT tools
Compile and synthesize Xilinx Vitis hello world vector addition testcase:
paolini@aptd:~/compe596/Vitis_Accel_Examples/hello_world$ make all TARGET=hw PLATFORM=/opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm
mkdir -p ./_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1
v++ -c --save-temps -t hw --platform /opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm -k vadd --temp_dir ./_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1 -I'src' -o'_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.xo' 'src/vadd.cpp'
Option Map File Used: '/tools/Xilinx/Vitis/2022.2/data/vitis/vpp/optMap.xml'
****** v++ v2022.2 (64-bit)
**** SW Build 3671529 on 2022-10-13-17:52:11
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ compile can be found at:
Reports: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/reports/vadd
Log files: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/logs/vadd
Running Dispatch Server on port: 35571
INFO: [v++ 60-1548] Creating build summary session with primary output /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.xo.compile_summary, at Thu Dec 15 16:32:31 2022
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/reports/vadd/v++_compile_vadd_guidance.html', at Thu Dec 15 16:32:31 2022
INFO: [v++ 60-895] Target platform: /opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/hw/hw.xsa'
INFO: [v++ 74-78] Compiler Version string: 2022.2
INFO: [v++ 60-585] Compiling for hardware target
INFO: [v++ 60-423] Target device: xilinx_u280_gen3x16_xdma_1_202211_1
INFO: [v++ 60-242] Creating kernel: 'vadd'
===>The following messages were generated while performing high-level synthesis for kernel: vadd Log file: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd/vadd/vitis_hls.log :
INFO: [v++ 204-61] Pipelining loop 'mem_rd'.
INFO: [v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 3, loop 'mem_rd'
INFO: [v++ 204-61] Pipelining loop 'mem_rd'.
INFO: [v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 3, loop 'mem_rd'
INFO: [v++ 204-61] Pipelining loop 'execute'.
INFO: [v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 3, loop 'execute'
INFO: [v++ 204-61] Pipelining loop 'mem_wr'.
INFO: [v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 3, loop 'mem_wr'
INFO: [v++ 200-789] **** Estimated Fmax: 411.00 MHz
INFO: [v++ 60-594] Finished kernel compilation
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/reports/vadd/system_estimate_vadd.xtxt
INFO: [v++ 60-586] Created _x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.xo
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command.
vitis_analyzer /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.xo.compile_summary
INFO: [v++ 60-791] Total elapsed time: 0h 0m 55s
INFO: [v++ 60-1653] Closing dispatch client.
mkdir -p ./build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1
v++ -l --save-temps -t hw --platform /opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm --temp_dir ./_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1 -o'./build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.link.xclbin' _x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.xo
Option Map File Used: '/tools/Xilinx/Vitis/2022.2/data/vitis/vpp/optMap.xml'
****** v++ v2022.2 (64-bit)
**** SW Build 3671529 on 2022-10-13-17:52:11
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
Reports: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/reports/link
Log files: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/logs/link
Running Dispatch Server on port: 39537
INFO: [v++ 60-1548] Creating build summary session with primary output /home/paolini/compe596/Vitis_Accel_Examples/hello_world/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.link.xclbin.link_summary, at Thu Dec 15 16:33:29 2022
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/reports/link/v++_link_vadd.link_guidance.html', at Thu Dec 15 16:33:29 2022
INFO: [v++ 60-895] Target platform: /opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/hw/hw.xsa'
INFO: [v++ 74-78] Compiler Version string: 2022.2
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423] Target device: xilinx_u280_gen3x16_xdma_1_202211_1
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [16:33:32] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.xo -keep --xpfm /opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm --target hw --output_dir /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int --temp_dir /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/run_link
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [16:33:34] build_xd_ip_db started: /tools/Xilinx/Vitis/2022.2/bin/build_xd_ip_db -ip_search 0 -sds-pf /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link/hw.hpfm -clkid 0 -ip /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link/iprepo/xilinx_com_hls_vadd_1_0,vadd -o /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [16:33:38] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 429.152 ; gain = 0.000 ; free physical = 506239 ; free virtual = 510916
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [16:33:38] cfgen started: /tools/Xilinx/Vitis/2022.2/bin/cfgen -dpa_mem_offload false -dmclkid 0 -r /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs:
INFO: [CFGEN 83-0] kernel: vadd, num: 1 {vadd_1}
INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.in1 to HBM[0]
INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.out to HBM[0]
INFO: [CFGEN 83-2226] Inferring mapping for argument vadd_1.in2 to HBM[0]
INFO: [SYSTEM_LINK 82-37] [16:33:48] cfgen finished successfully
Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 429.152 ; gain = 0.000 ; free physical = 506242 ; free virtual = 510919
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [16:33:48] cf2bd started: /tools/Xilinx/Vitis/2022.2/bin/cf2bd --linux --trace_buffer 1024 --input_file /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link/_sysl/.xsd --temp_dir /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link --output_dir /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int --target_bd ulp.bd
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -bd ulp.bd -dn dr -dp /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/sys_link/_sysl/.xsd
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [16:33:52] cf2bd finished successfully
Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 429.152 ; gain = 0.000 ; free physical = 506237 ; free virtual = 510920
INFO: [v++ 60-1441] [16:33:52] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 506297 ; free virtual = 510979
INFO: [v++ 60-1443] [16:33:52] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/sdsl.dat -rtd /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/cf2sw.rtd -nofilter /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/cf2sw_full.rtd -xclbin /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/xclbin_orig.xml -o /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/run_link
INFO: [v++ 60-1441] [16:33:57] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 506298 ; free virtual = 510981
INFO: [v++ 60-1443] [16:33:57] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram
INFO: [v++ 60-1454] Run Directory: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/run_link
INFO: [v++ 60-1441] [16:33:58] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.27 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 506277 ; free virtual = 510960
INFO: [v++ 60-1443] [16:33:58] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm -s --remote_ip_cache /home/paolini/compe596/Vitis_Accel_Examples/hello_world/.ipcache --output_dir /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int --log_dir /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/logs/link --report_dir /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/reports/link --config /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/vplConfig.ini -k /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link --no-info --iprepo /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/xo/ip_repo/xilinx_com_hls_vadd_1_0 --messageDb /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/run_link/vpl.pb /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/run_link
****** vpl v2022.2 (64-bit)
**** SW Build 3671529 on 2022-10-13-17:52:11
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
INFO: [VPL 60-839] Read in kernel information from file '/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/kernel_info.dat'.
INFO: [VPL 74-78] Compiler Version string: 2022.2
INFO: [VPL 60-423] Target device: xilinx_u280_gen3x16_xdma_1_202211_1
INFO: [VPL 60-1032] Extracting hardware platform to /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/vivado/vpl/.local/hw_platform
[16:34:10] Run vpl: Step create_project: Started
Creating Vivado project.
[16:34:17] Run vpl: Step create_project: Completed
[16:34:17] Run vpl: Step create_bd: Started
[16:34:44] Run vpl: Step create_bd: Completed
[16:34:44] Run vpl: Step update_bd: Started
[16:34:45] Run vpl: Step update_bd: Completed
[16:34:45] Run vpl: Step generate_target: Started
[16:35:39] Run vpl: Step generate_target: Completed
[16:35:39] Run vpl: Step config_hw_runs: Started
[16:35:41] Run vpl: Step config_hw_runs: Completed
[16:35:41] Run vpl: Step synth: Started
[16:36:12] Block-level synthesis in progress, 0 of 1 jobs complete, 1 job running.
[16:36:42] Block-level synthesis in progress, 0 of 1 jobs complete, 1 job running.
[16:37:10] Run vpl: Step synth: Completed
[16:37:10] Run vpl: Step impl: Started
[16:45:41] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 11m 42s
[16:45:41] Starting logic optimization..
[16:47:12] Phase 1 Retarget
[16:47:12] Phase 2 Constant propagation
[16:47:42] Phase 3 Sweep
[16:48:12] Phase 4 BUFG optimization
[16:48:12] Phase 5 Shift Register Optimization
[16:48:12] Phase 6 Post Processing Netlist
[16:49:12] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 03m 30s
[16:49:12] Starting logic placement..
[16:49:42] Phase 1 Placer Initialization
[16:49:42] Phase 1.1 Placer Initialization Netlist Sorting
[16:53:43] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[16:54:13] Phase 1.3 Build Placer Netlist Model
[16:56:13] Phase 1.4 Constrain Clocks/Macros
[16:56:13] Phase 2 Global Placement
[16:56:13] Phase 2.1 Floorplanning
[16:57:13] Phase 2.1.1 Partition Driven Placement
[16:57:13] Phase 2.1.1.1 PBP: Partition Driven Placement
[16:57:13] Phase 2.1.1.2 PBP: Clock Region Placement
[16:57:44] Phase 2.1.1.3 PBP: Compute Congestion
[16:58:14] Phase 2.1.1.4 PBP: UpdateTiming
[16:58:14] Phase 2.1.1.5 PBP: Add part constraints
[16:58:14] Phase 2.2 Physical Synthesis After Floorplan
[16:58:44] Phase 2.3 Update Timing before SLR Path Opt
[16:58:44] Phase 2.4 Post-Processing in Floorplanning
[16:58:44] Phase 2.5 Global Placement Core
[17:10:17] Phase 2.5.1 UpdateTiming Before Physical Synthesis
[17:10:47] Phase 2.5.2 Physical Synthesis In Placer
[17:12:18] Phase 3 Detail Placement
[17:12:18] Phase 3.1 Commit Multi Column Macros
[17:12:18] Phase 3.2 Commit Most Macros & LUTRAMs
[17:13:18] Phase 3.3 Small Shape DP
[17:13:18] Phase 3.3.1 Small Shape Clustering
[17:13:48] Phase 3.3.2 Flow Legalize Slice Clusters
[17:13:48] Phase 3.3.3 Slice Area Swap
[17:13:48] Phase 3.3.3.1 Slice Area Swap Initial
[17:14:49] Phase 3.4 Place Remaining
[17:14:49] Phase 3.5 Re-assign LUT pins
[17:14:49] Phase 3.6 Pipeline Register Optimization
[17:14:49] Phase 3.7 Fast Optimization
[17:15:49] Phase 4 Post Placement Optimization and Clean-Up
[17:15:49] Phase 4.1 Post Commit Optimization
[17:16:49] Phase 4.1.1 Post Placement Optimization
[17:16:49] Phase 4.1.1.1 BUFG Insertion
[17:16:49] Phase 1 Physical Synthesis Initialization
[17:17:19] Phase 4.1.1.2 BUFG Replication
[17:17:19] Phase 4.1.1.3 Post Placement Timing Optimization
[17:18:50] Phase 4.1.1.4 Replication
[17:19:50] Phase 4.2 Post Placement Cleanup
[17:19:50] Phase 4.3 Placer Reporting
[17:19:50] Phase 4.3.1 Print Estimated Congestion
[17:19:50] Phase 4.4 Final Placement Cleanup
[17:22:51] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 33m 39s
[17:22:51] Starting logic routing..
[17:23:21] Phase 1 Build RT Design
[17:24:52] Phase 2 Router Initialization
[17:24:52] Phase 2.1 Fix Topology Constraints
[17:24:52] Phase 2.2 Pre Route Cleanup
[17:25:22] Phase 2.3 Global Clock Net Routing
[17:25:52] Phase 2.4 Update Timing
[17:27:22] Phase 2.5 Update Timing for Bus Skew
[17:27:22] Phase 2.5.1 Update Timing
[17:27:53] Phase 3 Initial Routing
[17:27:53] Phase 3.1 Global Routing
[17:28:23] Phase 4 Rip-up And Reroute
[17:28:23] Phase 4.1 Global Iteration 0
[17:34:25] Phase 4.2 Global Iteration 1
[17:35:25] Phase 4.3 Global Iteration 2
[17:36:55] Phase 5 Delay and Skew Optimization
[17:36:55] Phase 5.1 Delay CleanUp
[17:36:55] Phase 5.1.1 Update Timing
[17:37:56] Phase 5.1.2 Update Timing
[17:38:26] Phase 5.2 Clock Skew Optimization
[17:38:26] Phase 6 Post Hold Fix
[17:38:26] Phase 6.1 Hold Fix Iter
[17:38:26] Phase 6.1.1 Update Timing
[17:38:56] Phase 7 Leaf Clock Prog Delay Opt
[17:39:56] Phase 8 Route finalize
[17:39:56] Phase 9 Verifying routed nets
[17:39:56] Phase 10 Depositing Routes
[17:40:27] Phase 11 Resolve XTalk
[17:40:27] Phase 12 Post Router Timing
[17:40:57] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 18m 05s
[17:40:57] Starting bitstream generation..
[17:49:29] Creating bitmap...
[18:04:04] Writing bitstream ./level0_i_ulp_my_rm_partial.bit...
[18:04:04] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 23m 07s
Check VPL, containing 1 checks, has run: 0 errors
[18:05:03] Run vpl: Step impl: Completed
[18:05:03] Run vpl: FINISHED. Run Status: impl Complete!
INFO: [v++ 60-1441] [18:05:03] Run run_link: Step vpl: Completed
Time (s): cpu = 00:00:27 ; elapsed = 01:31:06 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 502156 ; free virtual = 507926
INFO: [v++ 60-1443] [18:05:04] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/run_link
INFO: [v++ 60-991] clock name 'ulp_ucs/aclk_kernel_01' (clock ID '1') is being mapped to clock name 'KERNEL_CLK' in the xclbin
INFO: [v++ 60-991] clock name 'ulp_ucs/aclk_kernel_00' (clock ID '0') is being mapped to clock name 'DATA_CLK' in the xclbin
INFO: [v++ 60-991] clock name 'hbm_aclk' (clock ID '') is being mapped to clock name 'hbm_aclk' in the xclbin
INFO: [v++ 60-1230] The compiler selected the following frequencies for the runtime controllable kernel clock(s) and scalable system clock(s): System (SYSTEM) clock: hbm_aclk = 450, Kernel (KERNEL) clock: ulp_ucs/aclk_kernel_01 = 500, Kernel (DATA) clock: ulp_ucs/aclk_kernel_00 = 300
INFO: [v++ 60-1453] Command Line: cf2sw -a /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/address_map.xml -sdsl /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/sdsl.dat -xclbin /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/xclbin_orig.xml -rtd /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/vadd.link.rtd -o /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/vadd.link.xml
INFO: [v++ 60-1652] Cf2sw returned exit code: 0
INFO: [v++ 60-1441] [18:05:08] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 502162 ; free virtual = 507933
INFO: [v++ 60-1443] [18:05:08] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/partial.bit --force --target hw --key-value SYS:dfx_enable:true --add-section :JSON:/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/vadd.link.rtd --append-section :JSON:/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/appendSection.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/vadd.link_xml.rtd --add-section BUILD_METADATA:JSON:/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/vadd.link_build.rtd --add-section EMBEDDED_METADATA:RAW:/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/vadd.link.xml --add-section SYSTEM_METADATA:RAW:/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:xilinx_u280_gen3x16_xdma_1_202211_1 --output /home/paolini/compe596/Vitis_Accel_Examples/hello_world/./build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.link.xclbin
INFO: [v++ 60-1454] Run Directory: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/run_link
XRT Build Version: 2.14.354 (2022.2)
Build Date: 2022-10-08 09:49:58
Hash ID: 43926231f7183688add2dccfd391b36a1f000bea
Creating a default 'in-memory' xclbin image.
Section: 'BITSTREAM'(0) was successfully added.
Size : 50480138 bytes
Format : RAW
File : '/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/partial.bit'
Section: 'MEM_TOPOLOGY'(6) was successfully added.
Format : JSON
File : 'mem_topology'
Section: 'IP_LAYOUT'(8) was successfully added.
Format : JSON
File : 'ip_layout'
Section: 'CONNECTIVITY'(7) was successfully added.
Format : JSON
File : 'connectivity'
Section: 'CLOCK_FREQ_TOPOLOGY'(11) was successfully added.
Size : 410 bytes
Format : JSON
File : '/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/vadd.link_xml.rtd'
Section: 'BUILD_METADATA'(14) was successfully added.
Size : 2357 bytes
Format : JSON
File : '/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/vadd.link_build.rtd'
Section: 'EMBEDDED_METADATA'(2) was successfully added.
Size : 7966 bytes
Format : RAW
File : '/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/vadd.link.xml'
Section: 'SYSTEM_METADATA'(22) was successfully added.
Size : 25255 bytes
Format : RAW
File : '/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/int/systemDiagramModelSlrBaseAddress.json'
Section: 'PARTITION_METADATA'(20) was successfully appended to.
Format : JSON
File : 'partition_metadata'
Section: 'IP_LAYOUT'(8) was successfully appended to.
Format : JSON
File : 'ip_layout'
Successfully wrote (50544313 bytes) to the output file: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/./build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.link.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [18:05:08] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.23 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 502118 ; free virtual = 507936
INFO: [v++ 60-1443] [18:05:08] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --force --info /home/paolini/compe596/Vitis_Accel_Examples/hello_world/./build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.link.xclbin.info --input /home/paolini/compe596/Vitis_Accel_Examples/hello_world/./build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.link.xclbin
INFO: [v++ 60-1454] Run Directory: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/run_link
INFO: [v++ 60-1441] [18:05:09] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.58 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 502119 ; free virtual = 507938
INFO: [v++ 60-1443] [18:05:09] Run run_link: Step generate_sc_driver: Started
INFO: [v++ 60-1453] Command Line:
INFO: [v++ 60-1454] Run Directory: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/link/run_link
INFO: [v++ 60-1441] [18:05:09] Run run_link: Step generate_sc_driver: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 502119 ; free virtual = 507938
Check POST-VPL, containing 1 checks, has run: 0 errors
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/reports/link/system_estimate_vadd.link.xtxt
INFO: [v++ 60-586] Created /home/paolini/compe596/Vitis_Accel_Examples/hello_world/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.link.ltx
INFO: [v++ 60-586] Created ./build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.link.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
Guidance: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/reports/link/v++_link_vadd.link_guidance.html
Timing Report: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/reports/link/imp/impl_1_hw_bb_locked_timing_summary_routed.rpt
Vivado Log: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/logs/link/vivado.log
Steps Log File: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1/logs/link/link.steps.log
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command.
vitis_analyzer /home/paolini/compe596/Vitis_Accel_Examples/hello_world/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.link.xclbin.link_summary
INFO: [v++ 60-791] Total elapsed time: 1h 31m 50s
INFO: [v++ 60-1653] Closing dispatch client.
v++ -p ./build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.link.xclbin --save-temps -t hw --platform /opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm --package.out_dir ./package.hw -o ./build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.xclbin
Option Map File Used: '/tools/Xilinx/Vitis/2022.2/data/vitis/vpp/optMap.xml'
****** v++ v2022.2 (64-bit)
**** SW Build 3671529 on 2022-10-13-17:52:11
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
INFO: [v++ 60-1306] Additional information associated with this v++ package can be found at:
Reports: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x/reports/package
Log files: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x/logs/package
Running Dispatch Server on port: 46753
INFO: [v++ 60-1548] Creating build summary session with primary output /home/paolini/compe596/Vitis_Accel_Examples/hello_world/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.xclbin.package_summary, at Thu Dec 15 18:05:31 2022
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/paolini/compe596/Vitis_Accel_Examples/hello_world/_x/reports/package/v++_package_vadd_guidance.html', at Thu Dec 15 18:05:31 2022
INFO: [v++ 60-895] Target platform: /opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm
INFO: [v++ 60-1578] This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/hw/hw.xsa'
INFO: [v++ 74-78] Compiler Version string: 2022.2
INFO: [v++ 60-2256] Packaging for hardware
INFO: [v++ 60-2460] Successfully copied a temporary xclbin to the output xclbin: /home/paolini/compe596/Vitis_Accel_Examples/hello_world/./build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.xclbin
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command.
vitis_analyzer /home/paolini/compe596/Vitis_Accel_Examples/hello_world/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.xclbin.package_summary
INFO: [v++ 60-791] Total elapsed time: 0h 0m 13s
INFO: [v++ 60-1653] Closing dispatch client.
emconfigutil --platform /opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm --od ./_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1
****** configutil v2022.2 (64-bit)
**** SW Build 3671529 on 2022-10-13-17:52:11
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
INFO: [ConfigUtil 60-895] Target platform: /opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm
INFO: [ConfigUtil 60-1578] This platform contains Xilinx Shell Archive '/opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/hw/hw.xsa'
INFO: [ConfigUtil 60-1032] Extracting hardware platform to ./_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1
emulation configuration file `emconfig.json` is created in ./_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1 directory
Verify Xilinx Vitis hello world vector addition testcase runs in hardware:
paolini@aptd:~/compe596/Vitis_Accel_Examples/hello_world$ make run TARGET=hw PLATFORM=/opt/xilinx/platforms/xilinx_u280_gen3x16_xdma_1_202211_1/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm
./hello_world ./build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.xclbin
Found Platform
Platform Name: Xilinx
INFO: Reading ./build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.xclbin
Loading: './build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1/vadd.xclbin'
Trying to program device[0]: xilinx_u280_gen3x16_xdma_base_1
Device[0]: program successful!
TEST PASSED
paolini@aptd:~/compe596/Vitis_Accel_Examples/hello_world$