{"id":556,"date":"2022-12-15T16:01:21","date_gmt":"2022-12-16T00:01:21","guid":{"rendered":"https:\/\/iotlab.sdsu.edu\/?page_id=556"},"modified":"2022-12-15T18:11:27","modified_gmt":"2022-12-16T02:11:27","slug":"flash-base-image-on-xilinx-alveo-u280","status":"publish","type":"page","link":"https:\/\/iotlab.sdsu.edu\/index.php\/flash-base-image-on-xilinx-alveo-u280\/","title":{"rendered":"Flash base image on Xilinx Alveo U280"},"content":{"rendered":"\n<p>Verify presence of the default &#8220;golden&#8221; shell using <em>xbmgmt  examine &#8211;verbose<\/em><\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>paolini@aptd:~$ sudo \/opt\/xilinx\/xrt\/bin\/xbmgmt examine --verbose\r\nVerbose: Enabling Verbosity\r\nVerbose: SubCommand: examine\r\nSystem Configuration\r\n  OS Name              : Linux\r\n  Release              : 5.4.0-135-generic\r\n  Version              : #152-Ubuntu SMP Wed Nov 23 20:19:22 UTC 2022\r\n  Machine              : x86_64\r\n  CPU Cores            : 128\r\n  Memory               : 515894 MB\r\n  Distribution         : Ubuntu 20.04.5 LTS\r\n  GLIBC                : 2.31\r\n  Model                : R282-Z93-00\r\n\r\nXRT\r\n  Version              : 2.14.354\r\n  Branch               : 2022.2\r\n  Hash                 : 43926231f7183688add2dccfd391b36a1f000bea\r\n  Hash Date            : 2022-10-08 09:49:58\r\n  XOCL                 : unknown, unknown\r\n  XCLMGMT              : 2.14.354, 43926231f7183688add2dccfd391b36a1f000bea\r\n\r\nDevices present\r\nBDF             :  Shell                 Platform UUID  Device ID  Device Ready*\r\n----------------------------------------------------------------------------------\r\n&#91;0000:81:00.0]  :  <strong>xilinx_u280_GOLDEN_8<\/strong>  n\/a            n\/a        No\r\n\r\n\r\n* Devices that are not ready will have reduced functionality when using XRT tools\r\n<\/code><\/pre>\n\n\n\n<p>Then flash the base image using <em>xbmgmt program &#8211;base &#8211;device 0000:81:00.0 &#8211;image \/opt\/xilinx\/firmware\/u280\/gen3x16-xdma\/base\/partition.xsabin<\/em><\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>paolini@aptd:~$ sudo \/opt\/xilinx\/xrt\/bin\/xbmgmt program --base --device 0000:81:00.0 --image \/opt\/xilinx\/firmware\/u280\/gen3x16-xdma\/base\/partition.xsabin\r\n----------------------------------------------------\r\nDevice : &#91;0000:81:00.0]\r\n\r\nCurrent Configuration\r\n  Platform             : xilinx_u280_GOLDEN_8\r\n  SC Version           : INACTIVE\r\n  Platform ID          : N\/A\r\n\r\n\r\nIncoming Configuration\r\n  Deployment File      : partition.xsabin\r\n  Deployment Directory : \/lib\/firmware\/xilinx\/283bab8f654d8674968f4da57f7fa5d7\r\n  Size                 : 135,050,025 bytes\r\n  Timestamp            : Sun Dec  4 21:36:42 2022\r\n\r\n  Platform             : xilinx_u280_gen3x16_xdma_base_1\r\n  SC Version           : 4.3.28\r\n  Platform UUID        : 283BAB8F-654D-8674-968F-4DA57F7FA5D7\r\n----------------------------------------------------\r\nActions to perform:\r\n  &#91;0000:81:00.0] : Program base (FLASH) image\r\n----------------------------------------------------\r\nAre you sure you wish to proceed? &#91;Y\/n]: y\r\n\r\n&#91;0000:81:00.0] : Updating base (e.g., shell) flash image...\r\nBitstream guard installed on flash @0x1002000\r\nPersisted 716129 bytes of meta data to flash 0 @0x7f51273\r\nExtracting bitstream from MCS data:\r\n...............................................\r\nExtracted 48844316 bytes from bitstream @0x1002000\r\nWriting bitstream to flash 0:\r\n...............................................\r\nBitstream guard removed from flash\r\nINFO     : Base flash image has been programmed successfully.\r\n----------------------------------------------------\r\nReport\r\n  &#91;0000:81:00.0] : Factory or Recovery image detected. Reflash the device after the reboot to update the SC firmware.\r\n  &#91;0000:81:00.0] : Successfully flashed the base (e.g., shell) image\r\n\r\nDevice flashed successfully.\r\n****************************************************\r\nCold reboot machine to load the new image on device.\r\n****************************************************\r<\/code><\/pre>\n\n\n\n<p>After a cold reboot, verify presence of new SC firmware and device is ready:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>paolini@aptd:~$ sudo \/opt\/xilinx\/xrt\/bin\/xbmgmt  examine --verbose\r\nVerbose: Enabling Verbosity\r\nVerbose: SubCommand: examine\r\nSystem Configuration\r\n  OS Name              : Linux\r\n  Release              : 5.4.0-135-generic\r\n  Version              : #152-Ubuntu SMP Wed Nov 23 20:19:22 UTC 2022\r\n  Machine              : x86_64\r\n  CPU Cores            : 128\r\n  Memory               : 515894 MB\r\n  Distribution         : Ubuntu 20.04.5 LTS\r\n  GLIBC                : 2.31\r\n  Model                : R282-Z93-00\r\n\r\nXRT\r\n  Version              : 2.14.354\r\n  Branch               : 2022.2\r\n  Hash                 : 43926231f7183688add2dccfd391b36a1f000bea\r\n  Hash Date            : 2022-10-08 09:49:58\r\n  XOCL                 : 2.14.354, 43926231f7183688add2dccfd391b36a1f000bea\r\n  XCLMGMT              : 2.14.354, 43926231f7183688add2dccfd391b36a1f000bea\r\n\r\nDevices present\r\nBDF             :  Shell                            Platform UUID                         Device ID         Device Ready*\r\n---------------------------------------------------------------------------------------------------------------------------\r\n&#91;0000:81:00.0]  :  xilinx_u280_gen3x16_xdma_base_1  283BAB8F-654D-8674-968F-4DA57F7FA5D7  mgmt(inst=33024)  Yes\r\n\r\n\r\n* Devices that are not ready will have reduced functionality when using XRT tools\r<\/code><\/pre>\n\n\n\n<p>Compile and synthesize Xilinx Vitis <em>hello world<\/em> vector addition testcase:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>paolini@aptd:~\/compe596\/Vitis_Accel_Examples\/hello_world$ make all TARGET=hw PLATFORM=\/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm\nmkdir -p .\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\r\nv++ -c --save-temps  -t hw --platform \/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm -k vadd --temp_dir .\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1  -I'src' -o'_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.xo' 'src\/vadd.cpp'\r\nOption Map File Used: '\/tools\/Xilinx\/Vitis\/2022.2\/data\/vitis\/vpp\/optMap.xml'\r\n\r\n****** v++ v2022.2 (64-bit)\n  **** SW Build 3671529 on 2022-10-13-17:52:11\r\n    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.\r\n\r\nINFO: &#91;v++ 60-1306] Additional information associated with this v++ compile can be found at:\r\n        Reports: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/reports\/vadd\r\n        Log files: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/logs\/vadd\r\nRunning Dispatch Server on port: 35571\r\nINFO: &#91;v++ 60-1548] Creating build summary session with primary output \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.xo.compile_summary, at Thu Dec 15 16:32:31 2022\r\nINFO: &#91;v++ 60-1315] Creating rulecheck session with output '\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/reports\/vadd\/v++_compile_vadd_guidance.html', at Thu Dec 15 16:32:31 2022\r\nINFO: &#91;v++ 60-895]   Target platform: \/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm\r\nINFO: &#91;v++ 60-1578]   This platform contains Xilinx Shell Archive '\/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/hw\/hw.xsa'\r\nINFO: &#91;v++ 74-78] Compiler Version string: 2022.2\r\nINFO: &#91;v++ 60-585] Compiling for hardware target\r\nINFO: &#91;v++ 60-423]   Target device: xilinx_u280_gen3x16_xdma_1_202211_1\r\nINFO: &#91;v++ 60-242] Creating kernel: 'vadd'\r\n\r\n===>The following messages were generated while  performing high-level synthesis for kernel: vadd Log file: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd\/vadd\/vitis_hls.log :\r\nINFO: &#91;v++ 204-61] Pipelining loop 'mem_rd'.\r\nINFO: &#91;v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 3, loop 'mem_rd'\r\nINFO: &#91;v++ 204-61] Pipelining loop 'mem_rd'.\r\nINFO: &#91;v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 3, loop 'mem_rd'\r\nINFO: &#91;v++ 204-61] Pipelining loop 'execute'.\r\nINFO: &#91;v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 3, loop 'execute'\r\nINFO: &#91;v++ 204-61] Pipelining loop 'mem_wr'.\r\nINFO: &#91;v++ 200-1470] Pipelining result : Target II = NA, Final II = 1, Depth = 3, loop 'mem_wr'\r\nINFO: &#91;v++ 200-789] **** Estimated Fmax: 411.00 MHz\r\nINFO: &#91;v++ 60-594] Finished kernel compilation\r\nINFO: &#91;v++ 60-244] Generating system estimate report...\r\nINFO: &#91;v++ 60-1092] Generated system estimate report: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/reports\/vadd\/system_estimate_vadd.xtxt\r\nINFO: &#91;v++ 60-586] Created _x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.xo\r\nINFO: &#91;v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command.\r\n    vitis_analyzer \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.xo.compile_summary\r\nINFO: &#91;v++ 60-791] Total elapsed time: 0h 0m 55s\r\nINFO: &#91;v++ 60-1653] Closing dispatch client.\r\nmkdir -p .\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\r\nv++ -l --save-temps   -t hw --platform \/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm --temp_dir .\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1 -o'.\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.link.xclbin' _x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.xo\r\nOption Map File Used: '\/tools\/Xilinx\/Vitis\/2022.2\/data\/vitis\/vpp\/optMap.xml'\r\n\r\n****** v++ v2022.2 (64-bit)\r\n  **** SW Build 3671529 on 2022-10-13-17:52:11\r\n    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.\r\n\r\nINFO: &#91;v++ 60-1306] Additional information associated with this v++ link can be found at:\r\n        Reports: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/reports\/link\r\n        Log files: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/logs\/link\r\nRunning Dispatch Server on port: 39537\r\nINFO: &#91;v++ 60-1548] Creating build summary session with primary output \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.link.xclbin.link_summary, at Thu Dec 15 16:33:29 2022\r\nINFO: &#91;v++ 60-1315] Creating rulecheck session with output '\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/reports\/link\/v++_link_vadd.link_guidance.html', at Thu Dec 15 16:33:29 2022\r\nINFO: &#91;v++ 60-895]   Target platform: \/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm\r\nINFO: &#91;v++ 60-1578]   This platform contains Xilinx Shell Archive '\/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/hw\/hw.xsa'\r\nINFO: &#91;v++ 74-78] Compiler Version string: 2022.2\r\nINFO: &#91;v++ 60-629] Linking for hardware target\r\nINFO: &#91;v++ 60-423]   Target device: xilinx_u280_gen3x16_xdma_1_202211_1\r\nINFO: &#91;v++ 60-1332] Run 'run_link' status: Not started\r\nINFO: &#91;v++ 60-1443] &#91;16:33:32] Run run_link: Step system_link: Started\r\nINFO: &#91;v++ 60-1453] Command Line: system_link --xo \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.xo -keep --xpfm \/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm --target hw --output_dir \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int --temp_dir \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link\r\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/run_link\r\nINFO: &#91;SYSTEM_LINK 82-70] Extracting xo v3 file \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.xo\r\nINFO: &#91;SYSTEM_LINK 82-53] Creating IP database \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link\/_sysl\/.cdb\/xd_ip_db.xml\r\nINFO: &#91;SYSTEM_LINK 82-38] &#91;16:33:34] build_xd_ip_db started: \/tools\/Xilinx\/Vitis\/2022.2\/bin\/build_xd_ip_db -ip_search 0  -sds-pf \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link\/hw.hpfm -clkid 0 -ip \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link\/iprepo\/xilinx_com_hls_vadd_1_0,vadd -o \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link\/_sysl\/.cdb\/xd_ip_db.xml\r\nINFO: &#91;SYSTEM_LINK 82-37] &#91;16:33:38] build_xd_ip_db finished successfully\r\nTime (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 429.152 ; gain = 0.000 ; free physical = 506239 ; free virtual = 510916\r\nINFO: &#91;SYSTEM_LINK 82-51] Create system connectivity graph\r\nINFO: &#91;SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link\/cfgraph\/cfgen_cfgraph.xml\r\nINFO: &#91;SYSTEM_LINK 82-38] &#91;16:33:38] cfgen started: \/tools\/Xilinx\/Vitis\/2022.2\/bin\/cfgen  -dpa_mem_offload false -dmclkid 0 -r \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link\/_sysl\/.cdb\/xd_ip_db.xml -o \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link\/cfgraph\/cfgen_cfgraph.xml\r\nINFO: &#91;CFGEN 83-0] Kernel Specs:\r\nINFO: &#91;CFGEN 83-0]   kernel: vadd, num: 1  {vadd_1}\r\nINFO: &#91;CFGEN 83-2226] Inferring mapping for argument vadd_1.in1 to HBM&#91;0]\r\nINFO: &#91;CFGEN 83-2226] Inferring mapping for argument vadd_1.out to HBM&#91;0]\r\nINFO: &#91;CFGEN 83-2226] Inferring mapping for argument vadd_1.in2 to HBM&#91;0]\r\nINFO: &#91;SYSTEM_LINK 82-37] &#91;16:33:48] cfgen finished successfully\r\nTime (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 429.152 ; gain = 0.000 ; free physical = 506242 ; free virtual = 510919\r\nINFO: &#91;SYSTEM_LINK 82-52] Create top-level block diagram\r\nINFO: &#91;SYSTEM_LINK 82-38] &#91;16:33:48] cf2bd started: \/tools\/Xilinx\/Vitis\/2022.2\/bin\/cf2bd  --linux --trace_buffer 1024 --input_file \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link\/cfgraph\/cfgen_cfgraph.xml --ip_db \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link\/_sysl\/.cdb\/xd_ip_db.xml --cf_name dr --working_dir \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link\/_sysl\/.xsd --temp_dir \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link --output_dir \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int --target_bd ulp.bd\r\nINFO: &#91;CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link\/cfgraph\/cfgen_cfgraph.xml -r \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link\/_sysl\/.cdb\/xd_ip_db.xml -o dr.xml\r\nINFO: &#91;CF2BD 82-28] cf2xd finished successfully\r\nINFO: &#91;CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -bd ulp.bd -dn dr -dp \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/sys_link\/_sysl\/.xsd\r\nINFO: &#91;CF2BD 82-28] cf_xsd finished successfully\r\nINFO: &#91;SYSTEM_LINK 82-37] &#91;16:33:52] cf2bd finished successfully\r\nTime (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 429.152 ; gain = 0.000 ; free physical = 506237 ; free virtual = 510920\r\nINFO: &#91;v++ 60-1441] &#91;16:33:52] Run run_link: Step system_link: Completed\r\nTime (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 506297 ; free virtual = 510979\r\nINFO: &#91;v++ 60-1443] &#91;16:33:52] Run run_link: Step cf2sw: Started\r\nINFO: &#91;v++ 60-1453] Command Line: cf2sw -sdsl \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/sdsl.dat -rtd \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/cf2sw.rtd -nofilter \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/cf2sw_full.rtd -xclbin \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/xclbin_orig.xml -o \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/xclbin_orig.1.xml\r\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/run_link\r\nINFO: &#91;v++ 60-1441] &#91;16:33:57] Run run_link: Step cf2sw: Completed\r\nTime (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 506298 ; free virtual = 510981\r\nINFO: &#91;v++ 60-1443] &#91;16:33:57] Run run_link: Step rtd2_system_diagram: Started\r\nINFO: &#91;v++ 60-1453] Command Line: rtd2SystemDiagram\r\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/run_link\r\nINFO: &#91;v++ 60-1441] &#91;16:33:58] Run run_link: Step rtd2_system_diagram: Completed\r\nTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.27 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 506277 ; free virtual = 510960\r\nINFO: &#91;v++ 60-1443] &#91;16:33:58] Run run_link: Step vpl: Started\r\nINFO: &#91;v++ 60-1453] Command Line: vpl -t hw -f \/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm -s --remote_ip_cache \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/.ipcache --output_dir \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int --log_dir \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/logs\/link --report_dir \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/reports\/link --config \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/vplConfig.ini -k \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/kernel_info.dat --webtalk_flag Vitis --temp_dir \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link --no-info --iprepo \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/xo\/ip_repo\/xilinx_com_hls_vadd_1_0 --messageDb \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/run_link\/vpl.pb \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/dr.bd.tcl\r\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/run_link\r\n\r\n****** vpl v2022.2 (64-bit)\r\n  **** SW Build 3671529 on 2022-10-13-17:52:11\r\n    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.\r\n\r\nINFO: &#91;VPL 60-839] Read in kernel information from file '\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/kernel_info.dat'.\r\nINFO: &#91;VPL 74-78] Compiler Version string: 2022.2\r\nINFO: &#91;VPL 60-423]   Target device: xilinx_u280_gen3x16_xdma_1_202211_1\r\nINFO: &#91;VPL 60-1032] Extracting hardware platform to \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/vivado\/vpl\/.local\/hw_platform\r\n&#91;16:34:10] Run vpl: Step create_project: Started\r\nCreating Vivado project.\r\n&#91;16:34:17] Run vpl: Step create_project: Completed\r\n&#91;16:34:17] Run vpl: Step create_bd: Started\r\n&#91;16:34:44] Run vpl: Step create_bd: Completed\r\n&#91;16:34:44] Run vpl: Step update_bd: Started\r\n&#91;16:34:45] Run vpl: Step update_bd: Completed\r\n&#91;16:34:45] Run vpl: Step generate_target: Started\r\n&#91;16:35:39] Run vpl: Step generate_target: Completed\r\n&#91;16:35:39] Run vpl: Step config_hw_runs: Started\r\n&#91;16:35:41] Run vpl: Step config_hw_runs: Completed\r\n&#91;16:35:41] Run vpl: Step synth: Started\r\n&#91;16:36:12] Block-level synthesis in progress, 0 of 1 jobs complete, 1 job running.\r\n&#91;16:36:42] Block-level synthesis in progress, 0 of 1 jobs complete, 1 job running.\r\n&#91;16:37:10] Run vpl: Step synth: Completed\r\n&#91;16:37:10] Run vpl: Step impl: Started\r\n&#91;16:45:41] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 11m 42s\r\n\r\n&#91;16:45:41] Starting logic optimization..\r\n&#91;16:47:12] Phase 1 Retarget\r\n&#91;16:47:12] Phase 2 Constant propagation\r\n&#91;16:47:42] Phase 3 Sweep\r\n&#91;16:48:12] Phase 4 BUFG optimization\r\n&#91;16:48:12] Phase 5 Shift Register Optimization\r\n&#91;16:48:12] Phase 6 Post Processing Netlist\r\n&#91;16:49:12] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 03m 30s\r\n\r\n&#91;16:49:12] Starting logic placement..\r\n&#91;16:49:42] Phase 1 Placer Initialization\r\n&#91;16:49:42] Phase 1.1 Placer Initialization Netlist Sorting\r\n&#91;16:53:43] Phase 1.2 IO Placement\/ Clock Placement\/ Build Placer Device\r\n&#91;16:54:13] Phase 1.3 Build Placer Netlist Model\r\n&#91;16:56:13] Phase 1.4 Constrain Clocks\/Macros\r\n&#91;16:56:13] Phase 2 Global Placement\r\n&#91;16:56:13] Phase 2.1 Floorplanning\r\n&#91;16:57:13] Phase 2.1.1 Partition Driven Placement\r\n&#91;16:57:13] Phase 2.1.1.1 PBP: Partition Driven Placement\r\n&#91;16:57:13] Phase 2.1.1.2 PBP: Clock Region Placement\r\n&#91;16:57:44] Phase 2.1.1.3 PBP: Compute Congestion\r\n&#91;16:58:14] Phase 2.1.1.4 PBP: UpdateTiming\r\n&#91;16:58:14] Phase 2.1.1.5 PBP: Add part constraints\r\n&#91;16:58:14] Phase 2.2 Physical Synthesis After Floorplan\r\n&#91;16:58:44] Phase 2.3 Update Timing before SLR Path Opt\r\n&#91;16:58:44] Phase 2.4 Post-Processing in Floorplanning\r\n&#91;16:58:44] Phase 2.5 Global Placement Core\r\n&#91;17:10:17] Phase 2.5.1 UpdateTiming Before Physical Synthesis\r\n&#91;17:10:47] Phase 2.5.2 Physical Synthesis In Placer\r\n&#91;17:12:18] Phase 3 Detail Placement\r\n&#91;17:12:18] Phase 3.1 Commit Multi Column Macros\r\n&#91;17:12:18] Phase 3.2 Commit Most Macros &amp; LUTRAMs\r\n&#91;17:13:18] Phase 3.3 Small Shape DP\r\n&#91;17:13:18] Phase 3.3.1 Small Shape Clustering\r\n&#91;17:13:48] Phase 3.3.2 Flow Legalize Slice Clusters\r\n&#91;17:13:48] Phase 3.3.3 Slice Area Swap\r\n&#91;17:13:48] Phase 3.3.3.1 Slice Area Swap Initial\r\n&#91;17:14:49] Phase 3.4 Place Remaining\r\n&#91;17:14:49] Phase 3.5 Re-assign LUT pins\r\n&#91;17:14:49] Phase 3.6 Pipeline Register Optimization\r\n&#91;17:14:49] Phase 3.7 Fast Optimization\r\n&#91;17:15:49] Phase 4 Post Placement Optimization and Clean-Up\r\n&#91;17:15:49] Phase 4.1 Post Commit Optimization\r\n&#91;17:16:49] Phase 4.1.1 Post Placement Optimization\r\n&#91;17:16:49] Phase 4.1.1.1 BUFG Insertion\r\n&#91;17:16:49] Phase 1 Physical Synthesis Initialization\r\n&#91;17:17:19] Phase 4.1.1.2 BUFG Replication\r\n&#91;17:17:19] Phase 4.1.1.3 Post Placement Timing Optimization\r\n&#91;17:18:50] Phase 4.1.1.4 Replication\r\n&#91;17:19:50] Phase 4.2 Post Placement Cleanup\r\n&#91;17:19:50] Phase 4.3 Placer Reporting\r\n&#91;17:19:50] Phase 4.3.1 Print Estimated Congestion\r\n&#91;17:19:50] Phase 4.4 Final Placement Cleanup\r\n&#91;17:22:51] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 33m 39s\r\n\r\n&#91;17:22:51] Starting logic routing..\r\n&#91;17:23:21] Phase 1 Build RT Design\r\n&#91;17:24:52] Phase 2 Router Initialization\r\n&#91;17:24:52] Phase 2.1 Fix Topology Constraints\r\n&#91;17:24:52] Phase 2.2 Pre Route Cleanup\r\n&#91;17:25:22] Phase 2.3 Global Clock Net Routing\r\n&#91;17:25:52] Phase 2.4 Update Timing\r\n&#91;17:27:22] Phase 2.5 Update Timing for Bus Skew\r\n&#91;17:27:22] Phase 2.5.1 Update Timing\r\n&#91;17:27:53] Phase 3 Initial Routing\r\n&#91;17:27:53] Phase 3.1 Global Routing\r\n&#91;17:28:23] Phase 4 Rip-up And Reroute\r\n&#91;17:28:23] Phase 4.1 Global Iteration 0\r\n&#91;17:34:25] Phase 4.2 Global Iteration 1\r\n&#91;17:35:25] Phase 4.3 Global Iteration 2\r\n&#91;17:36:55] Phase 5 Delay and Skew Optimization\r\n&#91;17:36:55] Phase 5.1 Delay CleanUp\r\n&#91;17:36:55] Phase 5.1.1 Update Timing\r\n&#91;17:37:56] Phase 5.1.2 Update Timing\r\n&#91;17:38:26] Phase 5.2 Clock Skew Optimization\r\n&#91;17:38:26] Phase 6 Post Hold Fix\r\n&#91;17:38:26] Phase 6.1 Hold Fix Iter\r\n&#91;17:38:26] Phase 6.1.1 Update Timing\r\n&#91;17:38:56] Phase 7 Leaf Clock Prog Delay Opt\r\n&#91;17:39:56] Phase 8 Route finalize\r\n&#91;17:39:56] Phase 9 Verifying routed nets\r\n&#91;17:39:56] Phase 10 Depositing Routes\r\n&#91;17:40:27] Phase 11 Resolve XTalk\r\n&#91;17:40:27] Phase 12 Post Router Timing\r\n&#91;17:40:57] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 18m 05s\r\n\r\n&#91;17:40:57] Starting bitstream generation..\r\n&#91;17:49:29] Creating bitmap...\r\n&#91;18:04:04] Writing bitstream .\/level0_i_ulp_my_rm_partial.bit...\r\n&#91;18:04:04] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 23m 07s\r\nCheck VPL, containing 1 checks, has run: 0 errors\r\n&#91;18:05:03] Run vpl: Step impl: Completed\r\n&#91;18:05:03] Run vpl: FINISHED. Run Status: impl Complete!\r\nINFO: &#91;v++ 60-1441] &#91;18:05:03] Run run_link: Step vpl: Completed\r\nTime (s): cpu = 00:00:27 ; elapsed = 01:31:06 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 502156 ; free virtual = 507926\r\nINFO: &#91;v++ 60-1443] &#91;18:05:04] Run run_link: Step rtdgen: Started\r\nINFO: &#91;v++ 60-1453] Command Line: rtdgen\r\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/run_link\r\nINFO: &#91;v++ 60-991] clock name 'ulp_ucs\/aclk_kernel_01' (clock ID '1') is being mapped to clock name 'KERNEL_CLK' in the xclbin\r\nINFO: &#91;v++ 60-991] clock name 'ulp_ucs\/aclk_kernel_00' (clock ID '0') is being mapped to clock name 'DATA_CLK' in the xclbin\r\nINFO: &#91;v++ 60-991] clock name 'hbm_aclk' (clock ID '') is being mapped to clock name 'hbm_aclk' in the xclbin\r\nINFO: &#91;v++ 60-1230] The compiler selected the following frequencies for the runtime controllable kernel clock(s) and scalable system clock(s): System (SYSTEM) clock: hbm_aclk = 450, Kernel (KERNEL) clock: ulp_ucs\/aclk_kernel_01 = 500, Kernel (DATA) clock: ulp_ucs\/aclk_kernel_00 = 300\r\nINFO: &#91;v++ 60-1453] Command Line: cf2sw -a \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/address_map.xml -sdsl \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/sdsl.dat -xclbin \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/xclbin_orig.xml -rtd \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/vadd.link.rtd -o \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/vadd.link.xml\r\nINFO: &#91;v++ 60-1652] Cf2sw returned exit code: 0\r\nINFO: &#91;v++ 60-1441] &#91;18:05:08] Run run_link: Step rtdgen: Completed\r\nTime (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 502162 ; free virtual = 507933\r\nINFO: &#91;v++ 60-1443] &#91;18:05:08] Run run_link: Step xclbinutil: Started\r\nINFO: &#91;v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/partial.bit --force --target hw --key-value SYS:dfx_enable:true --add-section :JSON:\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/vadd.link.rtd --append-section :JSON:\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/appendSection.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/vadd.link_xml.rtd --add-section BUILD_METADATA:JSON:\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/vadd.link_build.rtd --add-section EMBEDDED_METADATA:RAW:\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/vadd.link.xml --add-section SYSTEM_METADATA:RAW:\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:xilinx_u280_gen3x16_xdma_1_202211_1 --output \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/.\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.link.xclbin\r\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/run_link\r\nXRT Build Version: 2.14.354 (2022.2)\r\n       Build Date: 2022-10-08 09:49:58\r\n          Hash ID: 43926231f7183688add2dccfd391b36a1f000bea\r\nCreating a default 'in-memory' xclbin image.\r\n\r\nSection: 'BITSTREAM'(0) was successfully added.\r\nSize   : 50480138 bytes\r\nFormat : RAW\r\nFile   : '\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/partial.bit'\r\n\r\nSection: 'MEM_TOPOLOGY'(6) was successfully added.\r\nFormat : JSON\r\nFile   : 'mem_topology'\r\n\r\nSection: 'IP_LAYOUT'(8) was successfully added.\r\nFormat : JSON\r\nFile   : 'ip_layout'\r\n\r\nSection: 'CONNECTIVITY'(7) was successfully added.\r\nFormat : JSON\r\nFile   : 'connectivity'\r\n\r\nSection: 'CLOCK_FREQ_TOPOLOGY'(11) was successfully added.\r\nSize   : 410 bytes\r\nFormat : JSON\r\nFile   : '\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/vadd.link_xml.rtd'\r\n\r\nSection: 'BUILD_METADATA'(14) was successfully added.\r\nSize   : 2357 bytes\r\nFormat : JSON\r\nFile   : '\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/vadd.link_build.rtd'\r\n\r\nSection: 'EMBEDDED_METADATA'(2) was successfully added.\r\nSize   : 7966 bytes\r\nFormat : RAW\r\nFile   : '\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/vadd.link.xml'\r\n\r\nSection: 'SYSTEM_METADATA'(22) was successfully added.\r\nSize   : 25255 bytes\r\nFormat : RAW\r\nFile   : '\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/int\/systemDiagramModelSlrBaseAddress.json'\r\n\r\nSection: 'PARTITION_METADATA'(20) was successfully appended to.\r\nFormat : JSON\r\nFile   : 'partition_metadata'\r\n\r\nSection: 'IP_LAYOUT'(8) was successfully appended to.\r\nFormat : JSON\r\nFile   : 'ip_layout'\r\nSuccessfully wrote (50544313 bytes) to the output file: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/.\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.link.xclbin\r\nLeaving xclbinutil.\r\nINFO: &#91;v++ 60-1441] &#91;18:05:08] Run run_link: Step xclbinutil: Completed\r\nTime (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.23 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 502118 ; free virtual = 507936\r\nINFO: &#91;v++ 60-1443] &#91;18:05:08] Run run_link: Step xclbinutilinfo: Started\r\nINFO: &#91;v++ 60-1453] Command Line: xclbinutil --quiet --force --info \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/.\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.link.xclbin.info --input \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/.\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.link.xclbin\r\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/run_link\r\nINFO: &#91;v++ 60-1441] &#91;18:05:09] Run run_link: Step xclbinutilinfo: Completed\r\nTime (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.58 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 502119 ; free virtual = 507938\r\nINFO: &#91;v++ 60-1443] &#91;18:05:09] Run run_link: Step generate_sc_driver: Started\r\nINFO: &#91;v++ 60-1453] Command Line:\r\nINFO: &#91;v++ 60-1454] Run Directory: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/link\/run_link\r\nINFO: &#91;v++ 60-1441] &#91;18:05:09] Run run_link: Step generate_sc_driver: Completed\r\nTime (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 456.504 ; gain = 0.000 ; free physical = 502119 ; free virtual = 507938\r\nCheck POST-VPL, containing 1 checks, has run: 0 errors\r\nINFO: &#91;v++ 60-244] Generating system estimate report...\r\nINFO: &#91;v++ 60-1092] Generated system estimate report: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/reports\/link\/system_estimate_vadd.link.xtxt\r\nINFO: &#91;v++ 60-586] Created \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.link.ltx\r\nINFO: &#91;v++ 60-586] Created .\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.link.xclbin\r\nINFO: &#91;v++ 60-1307] Run completed. Additional information can be found in:\r\n        Guidance: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/reports\/link\/v++_link_vadd.link_guidance.html\r\n        Timing Report: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/reports\/link\/imp\/impl_1_hw_bb_locked_timing_summary_routed.rpt\r\n        Vivado Log: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/logs\/link\/vivado.log\r\n        Steps Log File: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/logs\/link\/link.steps.log\r\n\r\nINFO: &#91;v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command.\r\n    vitis_analyzer \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.link.xclbin.link_summary\r\nINFO: &#91;v++ 60-791] Total elapsed time: 1h 31m 50s\r\nINFO: &#91;v++ 60-1653] Closing dispatch client.\r\nv++ -p .\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.link.xclbin --save-temps  -t hw --platform \/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm --package.out_dir .\/package.hw -o .\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.xclbin\r\nOption Map File Used: '\/tools\/Xilinx\/Vitis\/2022.2\/data\/vitis\/vpp\/optMap.xml'\r\n\r\n****** v++ v2022.2 (64-bit)\r\n  **** SW Build 3671529 on 2022-10-13-17:52:11\r\n    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.\r\n\r\nINFO: &#91;v++ 60-1306] Additional information associated with this v++ package can be found at:\r\n        Reports: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x\/reports\/package\r\n        Log files: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x\/logs\/package\r\nRunning Dispatch Server on port: 46753\r\nINFO: &#91;v++ 60-1548] Creating build summary session with primary output \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.xclbin.package_summary, at Thu Dec 15 18:05:31 2022\r\nINFO: &#91;v++ 60-1315] Creating rulecheck session with output '\/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/_x\/reports\/package\/v++_package_vadd_guidance.html', at Thu Dec 15 18:05:31 2022\r\nINFO: &#91;v++ 60-895]   Target platform: \/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm\r\nINFO: &#91;v++ 60-1578]   This platform contains Xilinx Shell Archive '\/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/hw\/hw.xsa'\r\nINFO: &#91;v++ 74-78] Compiler Version string: 2022.2\r\nINFO: &#91;v++ 60-2256] Packaging for hardware\r\nINFO: &#91;v++ 60-2460] Successfully copied a temporary xclbin to the output xclbin: \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/.\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.xclbin\r\nINFO: &#91;v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command.\r\n    vitis_analyzer \/home\/paolini\/compe596\/Vitis_Accel_Examples\/hello_world\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.xclbin.package_summary\r\nINFO: &#91;v++ 60-791] Total elapsed time: 0h 0m 13s\r\nINFO: &#91;v++ 60-1653] Closing dispatch client.\r\nemconfigutil --platform \/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm --od .\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\r\n\r\n****** configutil v2022.2 (64-bit)\r\n  **** SW Build 3671529 on 2022-10-13-17:52:11\r\n    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.\r\n\r\nINFO: &#91;ConfigUtil 60-895]   Target platform: \/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm\r\nINFO: &#91;ConfigUtil 60-1578]   This platform contains Xilinx Shell Archive '\/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/hw\/hw.xsa'\r\nINFO: &#91;ConfigUtil 60-1032] Extracting hardware platform to .\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1\r\nemulation configuration file `emconfig.json` is created in .\/_x.hw.xilinx_u280_gen3x16_xdma_1_202211_1 directory\r<\/code><\/pre>\n\n\n\n<p>Verify Xilinx Vitis <em>hello world<\/em> vector addition testcase runs in hardware:<\/p>\n\n\n\n<pre class=\"wp-block-code\"><code>paolini@aptd:~\/compe596\/Vitis_Accel_Examples\/hello_world$ make run TARGET=hw PLATFORM=\/opt\/xilinx\/platforms\/xilinx_u280_gen3x16_xdma_1_202211_1\/xilinx_u280_gen3x16_xdma_1_202211_1.xpfm\r\n.\/hello_world .\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.xclbin\r\nFound Platform\r\nPlatform Name: Xilinx\r\nINFO: Reading .\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.xclbin\r\nLoading: '.\/build_dir.hw.xilinx_u280_gen3x16_xdma_1_202211_1\/vadd.xclbin'\r\nTrying to program device&#91;0]: xilinx_u280_gen3x16_xdma_base_1\r\nDevice&#91;0]: program successful!\r\n<strong>TEST PASSED\r\n<\/strong>paolini@aptd:~\/compe596\/Vitis_Accel_Examples\/hello_world$\r<\/code><\/pre>\n","protected":false},"excerpt":{"rendered":"<p>Verify presence of the default &#8220;golden&#8221; shell using xbmgmt examine &#8211;verbose Then flash the base image using xbmgmt program &#8211;base<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-556","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/iotlab.sdsu.edu\/index.php\/wp-json\/wp\/v2\/pages\/556","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/iotlab.sdsu.edu\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/iotlab.sdsu.edu\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/iotlab.sdsu.edu\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/iotlab.sdsu.edu\/index.php\/wp-json\/wp\/v2\/comments?post=556"}],"version-history":[{"count":8,"href":"https:\/\/iotlab.sdsu.edu\/index.php\/wp-json\/wp\/v2\/pages\/556\/revisions"}],"predecessor-version":[{"id":565,"href":"https:\/\/iotlab.sdsu.edu\/index.php\/wp-json\/wp\/v2\/pages\/556\/revisions\/565"}],"wp:attachment":[{"href":"https:\/\/iotlab.sdsu.edu\/index.php\/wp-json\/wp\/v2\/media?parent=556"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}